The Design of power harvester for passive RFID Tags

Abstract

This paper presents the design of a power harvester for passive RFID Tags. An impedance matching circuit chooses a high-pass L network inserted between the antenna and rectifier circuit to maximize the power transferred to Tags, using an impedance transformation technique. A simple circuit including only a shunt inductance was selected as a matching. The rectifier utilizes a Self-Vth-Cancellation (SVC) circuit is an archived self-threshold voltage cancellation and self-power regulation function with a simple circuit design. An antenna is modeled as an RF source with a series impedance Zs of 50Ω while the rectifier is modeled as a load impedance ZL, which is estimated from the process and design parameters of the NMOS and PMOS transistors used in the SVC rectifier. As the combined circuit was simulated using input in the UHF band of 953 MHz and the devices’ model of the 0.35μm CMOS technology. The simulation results were compared with the single-stage rectifier of the SVC technique in the issue of the Power Conversion Efficiency (PCE). The achieved DC output of the rectifier yields the power conversion efficiency of 43.7% at input RF power -10.22dBm while a DC output voltage of around 643.8mV and a current load of 64.4μA.